![]() ![]() VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 random: get_random_u32 called from bucket_table_alloc+0xfc/0x260 with crng_init=0 SMP: Total of 2 processors activated (400.00 BogoMIPS). ![]() Setting up static identity map for 0x100000 - 0x100060 Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) ![]() Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) Calibrating delay loop (skipped), value calculated using timer frequency. Switching to timer-based delay loop, resolution 10ns sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns clocksource: timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604467 ns L2C-310 cache controller enabled, 8 ways, 512 kB L2C-310 dynamic clock gating enabled, standby mode enabled L2C-310 ID prefetch enabled, offset 1 lines L2C-310: enabling full line of zeros but not enabled in Cortex-A9 L2C-310 enabling early BRESP for Cortex-A9 NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 ftrace: allocating 24189 entries in 71 pages SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) PID hash table entries: 4096 (order: 2, 16384 bytes) Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait Built 1 zonelists, mobility grouping on. Consider using a HIGHMEM enabled kernel. OF: fdt: Machine model: Altera SOCFPGA Arria 10 CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache CPU: ARMv7 Processor revision 1 (ARMv7), cr=10c5387d Loading Device Tree to 01ff1000, end 01fffefe. MMC: *** Warning - bad CRC, using default environmentįPGA must be in Early Release mode to program core.Ĥ523704 bytes read in 263 ms (16.4 MiB/s) Reserving 2048 Bytes for IRQ stack at: ffe386e8 INFO : Skip relocation as SDRAM is non secure memory JESD204 High-Speed Serial Interface Support JESD204 High-Speed Serial Interface Support -> Analog Devices AD9517 12-Output Clock Generator Analog Devices AD9548 Network Clock Generator/Synchronizer Analog Devices AD9528 Low Jitter Clock Generator Analog Devices AD9523 Low Jitter Clock Generator Analog Devices AD9508 Clock Fanout Buffer Analog Devices Motor Control (AD-FMCMOTCON) drivers Analog Devices AD6676 Wideband IF Receiver driver Analog Devices ADRV9009/ADRV9008 RF Transceiver driver Analog Devices AD9371 RF Transceiver driver Analog Devices AD9361, AD9364 RF Agile Transceiver driver *- Analog Devices High-Speed AXI ADC driver core *- Enable ring buffer support within IIO #make menuconfig Linux Kernel Configuration I wonder if the configuration for kernel is not correct, please help to check if I missed anything. But I can't find any info for 9009 with command "iio_info". I replace the zImage(from socfpga_arria10_socdk_adrv9009_2018_r2_rc3.zip) with the one I compiled. Now, I have checkout the 2018_R2 source code from github and compiled the linux kernel. I can see the info for 9009 with command "iio_info". My setup is Arria10+ADRV9009, and I use the following files and it works well.ġ. I have checked that link but it seems no details for Arria10 SOC. ![]()
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